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RISC-V only takes 12 years to achieve the milestone of 10 billion cores

RISC-V only takes 12 years to achieve the milestone of 10 billion cores, 5 years faster than ARM.

At the Embedded World conference held recently, Calista Redmond, CEO of RISC-V International, was pleased to announce that the number of cores in the RISC-V market has exceeded 10 billion.

Calista Redmond believes that open standards are the key to achieving this important milestone. “What Linux is doing for software is very similar to what we are doing for hardware,” she said. “We currently estimate the number of RISC-V cores in the market to exceed 10 billion.”

RISC-V is an open standard instruction set architecture (ISA) available under an open source license and is free to use.

The base instruction set has 32-bit fixed-length naturally aligned instructions, and the ISA supports variable-length extensions, which means that each instruction can be any digit length within a 16-bit packet.

The instruction set is available in 32-bit and 64-bit address space flavors and has been created for a wide range of uses.

Various subsets support everything from small embedded systems to PCs to supercomputers with vector processors to warehouse-scale rack-mounted parallel computers.

RISC-V only takes 12 years to achieve the milestone of 10 billion cores

The road to the tens of billions of cores is not an easy one. It is reported that the ARM architecture achieved this milestone in 2008 after 17 years of trial and error.

And RISC-V only took 12 years to complete tens of billions.

Redmond expects the number of RISC-V processor cores to reach 80 billion by 2025.

With this big positive news, 4 new specifications and extensions will be deployed this year.

The four new specifications are:

● SBI’s RISC-V specification uses an application installation interface in supervisor mode (S-mode or VS-mode) to build a firmware layer between the hardware platform and the operating system kernel.

This abstraction supports common platform services implemented across all RISC-V operating systems.

Many RISC-V members have already implemented the RISC-V SBI specification in their RISC-V solutions, so ratification of the specification will ensure a standard approach across the RISC-V ecosystem, ensuring compatibility.

The development and approval of this specification was led by Atish Patra of Rivos, with the work of the Platform Level Steering Committee.

● The RISC-V UEFI protocol brings the existing UEFI standard to the RISC-V platform.

The development and approval of this specification was led by Sunil VL, Ventana Micro and Philipp To MSI ch, VRULL GmbH, in the Privileged Software Technical Working Group.

● RISC-V’s E-Trace defines an efficient processor tracing method using branch tracing, ideal for debugging any type of application from tiny embedded designs to ultra-powerful computers.

The E-Trace of the RISC-V documentation specifies the signaling between the RISC-V core and the encoder (or ingress port), the compressed branch trace algorithm, and the packet format that encapsulates the compressed branch trace information.

Development and approval of the specification was led by Picocom’s Gajinder Panesar and RISC-V’s E-Trace Task Force.

● RISC-V Zmmul Multiply Only supports low-cost implementations that require multiplication but not division, and is part of the RISC-V unprivileged specification.

The development and approval of this extension was led by Allen Baum and the work was done on a non-privileged ISA committee.

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