RISC-V CPU architecture adds new specifications for more efficiency
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RISC-V CPU architecture adds new specifications for more efficiency.
As the third largest CPU architecture RISC-V impacting x86/ARM, it is being sought after by more manufacturers, so it is very necessary to improve it better.
RISC-V International has announced the approval of the first four specifications and extensions for 2022 – RISC-V Efficient Trace (E-Trace), RISC-V Supervisor Binary Interface (SBI), RISC-V Unified Extensible Firmware Interface (UEFI) specification, and the RISC-V Zmmul pure multiply extension.
“These new specifications accelerate the design of embedded and large systems,” said Mark Himelstein, CTO of RISC-V. “Debugging is one of the hardest things to do on a chip, and RISC-V’s E-Trace creates a standard way of tracing processors that is extremely efficient and especially useful in embedded system design.”
The RISC-V UEFI protocol brings the existing UEFI standard to the RISC-V platform.
The development and approval of the specification was led by Sunil VL of Ventana Micro and Philipp ToMSIch of VRULL GmbH, working in the Privileged Software Technical Working Group.
In this regard, experts say that for many microcontroller applications, the frequency of division operations is too low to justify the cost of divider hardware, and the RISC-V Zmmul extension will be particularly beneficial for simple FPGA soft cores.
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