The revolutionary PCIe 6.0 is coming: Support CXL3.0 high-speed interface
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The revolutionary PCIe 6.0 is coming: Support CXL3.0 high-speed interface.
Intel’s next-generation Xeon exposure: the first time the revolutionary PCIe 6.0 has landed.
On the desktop, Intel announced early on the Meteor Lakke 14th-generation Core, Arrow Lake 15th-generation Core, Lunar Lake 16th-generation Core, Nova Lake 17th-generation Core…
In the server data center, Intel Scalable Xeon also disclosed a long-term roadmap, including the fourth generation Sapphire Rapids (Intel 7 process), the fifth generation Dmerald Rapids (Intel 7 process), and the sixth generation Granite Rapids/Sierra Forest (Intel 7 process) 3 process / the latter size core), the seventh generation of Diamond Rapids.
However, Sapphire Rapids has been bouncing tickets endlessly, which has seriously affected the follow-up plan.
According to the exposure news, Diamond Rapids (DMR) will usher in a major change, supporting the PCIe 6.0 bus for the first time, and also supporting the CXL 3.0 high-speed interface for the first time, which is based on PCIe 6.0.
PCIe 6.0 was just officially released at the beginning of this year, CXL 3.0 was completed in August this year, and Diamond Rapids will arrive in 2025 at the earliest (probably later), that is, it will take at least three years before PCIe 6.0 will land.
PCIe 6.0 is considered to be the biggest change since the advent of PCIe nearly 20 years ago.
As usual, the bandwidth continues to double, and it can reach 256GB/s in both directions at full x16 speed.
At the same time, the pulse amplitude modulation signaling is changed from NRZ to PAM4, supplemented by FEC forward correction.
Wrong, the FLIT (Flow Control Unit) encoding was also upgraded at the logic layer.
In other respects, Diamond Rapids continues to support eight-channel DDR5 memory like the previous generation, optional HBM high-bandwidth memory, and integrated chipset.
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