Renesas’ World’s First PCIe 6.0 Timing Solution: 3 x 3 mm
2 min readRenesas’ World’s First PCIe 6.0 Timing Solution: 3 x 3 mm
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Renesas’ World’s First PCIe 6.0 Timing Solution: 3 x 3 mm
In January, the PCI-SIG organization officially released the PCIe 6.0 standard specification, the bandwidth continued to double, the x16 one-way can reach 128GB/s, and the PAM4 pulse amplitude modulation signaling, FEC forward error correction mechanism, and FLIT flow control unit encoding were upgraded. , is the greatest change in history.
Previously, Rambus was the first in the world to release a controller that was fully compliant with PCIe 6.0, supporting all new features.
Now, Japan’s Renesas Electronics has released the world’s first PCIe 6.0 standard timing solution, including 11 clock buffers, 4 multiplexers, and clock generators .
Provide a complete product line for data center, cloud computing, networking, high-speed industrial applications.
Renesas said that while PCIe 6.0 bandwidth is improved, clock jitter (ClockJitter) is required not to exceed 100fps RMS, while Renesas RC190xx series clock buffers and RC192xx series multiplexer clock jitter is only 4fps RMS, which is equal to almost no noise. .
At the same time, the input and output delay is 1.4ns, the output and output deviation is 35ps, and the power supply voltage rejection ratio (PSRR) is -80dB@100kHz, which can ensure sufficient system stability, and supports power outage tolerance (PDT), flexible start sequence (FSS) ) to ensure stability in a system state.
In addition, power consumption is also reduced by 30% compared to the previous generation.
Renesas’ PCIe 6.0 clock buffer is available with 4, 8, 13, 16, 20, and 24 outputs, and the multiplexer is available with 2, 4, 8, and 16 outputs. The package size is only 3 × 3 mm.
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