NVIDIA: The AD104 chip on RTX4080 with more transistors than GA102 on RTX4090.
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NVIDIA: The AD104 chip on RTX4080 with more transistors than GA102 on RTX4090.
Recently, NVIDIA released the Ada Lovelace GPU with 4nm architecture, and the first batch of three graphics cards, GeForce RTX 4090 / RTX 4080 16GB / RTX 4080 12GB, are equipped with AD102, AD103, and AD104 chips.
Ryan Smith of AnandTech has already obtained this. Complete information on several chips.
The areas of AD102, AD103, and AD104 are 608mm², 378.6mm² and 294.5mm² respectively, and the corresponding transistor numbers are 76.3 billion, 45.9 billion and 35.8 billion respectively.
The transistor density of AD103 and AD104 is the same, and the transistor density of AD102 is slightly higher. In terms of quantity, AD104 has 7.5 billion more transistors than GA102.
model | AD102 | AD103 | AD104 | |||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
process node | TSMC 4N | TSMC 4N | TSMC 4N | |||||||||||||||||||||||||||||
Number of transistors | 76.3 billion | 45.9 billion | 35.8 billion | |||||||||||||||||||||||||||||
Chip size | 608mm² | 378.6mm² | 294.5mm² | |||||||||||||||||||||||||||||
SM quantity | 144 | 80 | 60 | |||||||||||||||||||||||||||||
Number of CUDAs | 18432 | 10240 | 7680 | |||||||||||||||||||||||||||||
Number of Tensors | 576 | 320 | 240 | |||||||||||||||||||||||||||||
RT quantity | 144 | 80 | 60 | |||||||||||||||||||||||||||||
Number of ROPs | 192 | 112 | 80 | |||||||||||||||||||||||||||||
L2 cache | 96MB | 64MB | 48MB | |||||||||||||||||||||||||||||
Corresponding graphics card | RTX 4090 | RTX 4080 16GB | RTX 4080 12GB | |||||||||||||||||||||||||||||
Nvidia has made some architectural changes, such as removing NVLink on Ada Lovelace GPUs, freeing up more space.
At the same time, the L2 cache of the Ada Lovelace architecture GPU has also undergone great changes, and the capacity has been significantly increased.
The Ada Lovelace architecture uses the same TSMC (TSMC) 4N process as the Hopper architecture.
According to HKEPC, it is not the same as the N4 process generally believed to be a reduced version on the 5nm process node.
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