September 24, 2022

COSFONE

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Navi 31 based on RDNA 3 architecture supports PCIe 5.0

2 min read

Navi 31 based on RDNA 3 architecture supports PCIe 5.0



 

Navi 31 based on RDNA 3 architecture supports PCIe 5.0, AMD may launch the first consumer-grade PCIe 5.0 graphics card.

There has been more and more news about the Navi 3x series of GPUs recently, involving many details of the RDNA 3 architecture.

With AMD adding the GFX11 GPU ID, the Radeon RX 7000 series graphics cards are getting closer to consumers.

Recently, some netizens revealed that Navi 31 will support the PCIe 5.0 standard specification, and the Radeon RX 7900 XT is likely to be the first consumer graphics card to support PCIe 5.0.

 

Navi 31 based on RDNA 3 architecture supports PCIe 5.0, AMD may launch the first consumer-grade PCIe 5.0 graphics card.

 

AMD will launch heavyweight products this year, whether it is CPU or GPU.

At present, AMD has confirmed that the new generation of AM5 (LGA 1718) platform will support the PCIe 5.0 standard specification, and the Ryzen 7000 series CPU code-named Raphael and based on Zen 4 architecture is already on the way.

If the news this time is reliable, it means that AMD will support the PCIe 5.0 standard on desktop platforms, from CPUs, GPUs to motherboards this year.

 

AMD’s Navi 3x series GPUs are likely to all support the PCIe 5.0 standard specification, so the remaining question is whether AMD will continue to limit the number of PCIe lanes for some GPUs, especially low-end models.

For example, the Radeon RX 6500 XT equipped with Navi 24, because the interface is only PCIe 4.0 x4, once used on the old platform of PCIe 3.0, the performance will be greatly affected.

 

PCIe 5.0 is backward compatible with PCIe 4.0 and previous specifications, improving signal integrity and mechanical performance by changing electrical design.

The new standard reduces latency and reduces signal attenuation over long distances.

Compared with the previous PCIe 4.0, PCIe 5.0 still uses the same 128b/130b encoding method, target bit error rate (BER), signaling and scrambling scheme, etc., but changes the definition of EIEOS and data bit rate.

Therefore, PCIe 5.0 brings a higher transmission speed, and the x16 bandwidth (bidirectional) is increased from 64 GB/s of PCIe 4.0 to 128 GB/s, which increases the upper limit of the transmission rate of the device.

 



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