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Can “Gluing” various chips really save Moore’s Law?
The “splicing” chip seems to have become the new “fashion” in the chip circle.
Apple’s spring new product launch in March released the M1 Ultra, which “bonded” two M1 Max chips, claiming that its performance surpasses Intel’s top CPU i9-12900K and GPU performance ceiling NVIDIA RTX 3090.
NVIDIA also announced at the GTC in March that the Grace CPU super chip made of two CPUs “bonded” is expected to have 2 to 3 times the performance of the yet-to-be-released 5th generation top CPU.
Earlier, AMD also used the step of “bonding” in its EYPC series CPUs to reduce the cost of chip design by half.
It seems that the “bonding” of its own chips is no longer a problem, so can the chips with the best performance be selected from the global market and glued together to create a more powerful chip?
A few weeks ago, the “universal glue” that can realize chip interconnection appeared. Chip companies such as Intel, AMD, and TSMC jointly established a small chip interconnection industry alliance to customize the UCIe 1.0 (Universal Chiplet Interconnect Express) standard.
If the interconnection method of the same chip company (such as NVIDIA’s NVlink) is regarded as a glue that can only bond one material and a single function, then the proposal of the UCIe standard means that the chip universal glue that can realize various chip interconnections Emergence.
Does the chip universal glue have enough capacity to replace the ever-shrinking transistors and become the “life-sustaining pill” of Moore’s Law?
The real starting point of the “glue” chip era
The development of “glue” chips has been going on for some time, but the industry has always been independent.
Due to the lack of a unified interface standard, the “glue” chip ecology is difficult to build. Large companies have stopped moving forward, and small companies have not dared to take the first step.
For a long time, the continuous evolution of Moore’s Law has been regarded as the main way to improve chip performance.
After more than 40 years of development, the transistors that make up the chip are almost shrinking to the atomic level, not only facing the problem of physical limits that are difficult to break through, but also the input-output ratio of process upgrades has also dropped significantly.
The industry has begun to find new ways to improve product performance, such as , increasing transistor density by changing packaging.
Gordon, who proposed Moore’s Law, also realized the importance of packaging, writing in his paper: “It turns out that it may be more economical to build large systems with smaller functional modules, which will be packaged and interconnected separately. “
To put it simply, it is to integrate the previously produced chips into one package to reduce product development time and cost. These chip modules can be of different process nodes and are finally connected together by die-to-die method. A model similar to that formed by connecting chips with glue is called the Chiplet model in the industry.
Over the years, chip companies such as AMD, Intel, TSMC, Marvell, etc. have introduced some designs similar to chiplets.
For example, Intel adopted the chiplet method called Foveros and launched a 3D packaged CPU platform.
One 10nm processor core and four 22nm processor cores are packaged together; TSMC is also developing a technology called system-on-chip (SoIC).
In these technologies, die-to-die interconnection is critical, i.e. one needs to be “bonded” to another die, each containing an IP block with a physical interface, a common The interface enables the interconnection of two dies.
In the early exploration of Chiplet, many companies developed interconnects with proprietary interfaces to interconnect their own chip models.
Since Chiplet’s ultimate goal is to obtain high-quality and interoperable chip modules in-house or across multiple chip suppliers, further development of Chiplet depends on the emergence of a new method in the industry that can connect different chip models.
The standard interface is the chip “universal glue” that can bond various chip modules together.
At the beginning of March this year, the universal glue UCIe finally appeared, and the glue era of chips ushered in a new starting point.
The implementation of open standards in each industry will trigger the outbreak of this industry. Following this industry development law, UCIe is of great significance to the development of Chiplet and is an important symbol of the arrival of the Chiplet era.
Chiplet has been promoted in the industry for many years and has been publicizing it, but it has not promoted industrialization.
A large part of the reason is that it is waiting for the standard to be established. If you choose a wrong standard, the results will not be recognized by the market, and a lot of energy will be wasted.
However, before the establishment of UCIe, there were various interface types in the industry. Does the emergence of “universal glue” mean that the previous efforts of those chip companies that have explored in the chiplet field are in vain?
Chiplet just means that different chip modules are connected by means of advanced packaging. “In the early stage of Chiplet’s development, each company will independently invest and research Chiplet according to their own product needs. After each has achieved technological breakthroughs in some aspects, they will converge into industry standards. This is a normal development process.”
The formulation of the UCIe standard will definitely use some of the previously defined protocols and familiar protocols, but there are also some new standards and package integration methods that need to be redefined to achieve better interoperability. “UCIe does not overturn previous work in the industry, but standardizes the technology of chiplet interconnection.”
To understand the positive effect of UCIe on the Chiplet era, it can be compared with PCIe. At the protocol layer, UCIe can even be understood as an extension of PCIe on the micro interconnect structure.
The previous PCIe solved the problem of data transmission between computer systems and peripheral devices. UCIe solved the problem of data transmission between small chips and small chips, and the independent modules on the packaged chip.
If there is no unified electrical signal standard, it will not be formed. Multiple companies work together to complete the ecological cooperation of system integration. Without cooperation, it is difficult for a single company entering Chiplet to complete the ecological construction required for industry development.
In the PC era, the x86 system led by Intel has a series of standards, such as the PCIe standard, which allows other products to cooperate with Intel’s CPU. A series of standards for the x86 system have built the hardware system of the entire PC era.
In the Chiplet era, the logic of establishing an ecosystem in the PC era is actually reduced and engraved into the chip. As a chip combination, Chiplet also needs to rely on the UCIe standard to easily combine the chip designs of different companies into one chip. Ecology and drive the entire industry forward.
However, PCIe has experienced more than ten years of development before it has become mainstream. The emergence of UCIe1.0 is only the starting point of the Chiplet era, and there is still a long way to go before Chiplet truly becomes mainstream. Even as powerful as Intel, it takes a lot of time and effort to achieve mass production.
The realization of the process is the first difficulty, and no one is willing to bear the cost of the project
In fact, the biggest difficulty in the development of Chiplet is not in protocol formulation, but in product definition and manufacturing.
The purpose of unifying protocols and standards is to reduce R&D costs and accelerate market application.
Although the establishment of the UCIe unified standard has pointed out the direction for the industry, there are still many challenges in the process capability requirements and large-scale manufacturing links brought by specific physical layer indicators, such as the stacking of multi-layer materials in the package, from silicon to silicon The stacking of silicon, organic materials, metals and other materials.
Connecting these materials requires small leads and line widths, high complexity, high yields, and high costs.
Taking Intel’s EMIB as an example, from the public papers released by Intel, it can be found that EMIB faces many difficulties in process implementation, and requires the development of materials and processes.
The design of its silicon bridge requires understanding of materials, packaging, Senior engineers who understand the process and understand signal integrity come together to realize it.
In addition, wafer manufacturing materials and equipment need to be improved, and the time and cost are unaffordable except for Apple, Intel and other head chip companies.
Not only that, even with UCIe, the universal adhesive for chips, the problem of “where is the Chiplet” is difficult to solve.
After UCIe, Chiplet faces the question of who will take the first step, Chiplet suppliers and application vendors.
This is also a ‘chicken and egg’ problem. Chiplet suppliers are more concerned about who should bear the one-time engineering cost (NRE) of Chiplet, while application providers are worried about whether there are enough Chiplets available for application, and when the price-performance ratio of Chiplet products can be verified first.
Because of this, even with the UCIe standard, it is easy for everyone to stay in the wait-and-see stage, waiting for the first person to appear.
Continuing Moore’s Law, the universal plastic chip is not omnipotent
Aside from the process problems, the key to the popularity of chip universal glue is whether it can continue Moore’s Law to give chip companies greater value.
From the perspective of the industry chain, on the one hand, as the technological trend of the semiconductor industry, Chiplet requires each chip company to do the best work in its own position. The connection between companies will be tighter. On the other hand, chip glue seems to be rewriting the evaluation system or dimension of chip companies or chip products.
For a long time, the most advanced front-end wafer process node is often a symbol of the best performance of the chip, and the most advanced process node often leads the trend of chip performance development. But in the Chiplet era, the competitiveness of a single advanced process node may be replaced by multi-chip heterogeneous system integration, and heterogeneous integration capabilities have gradually become a new standard for evaluating a chip design or manufacturing company.
It is precisely because of this that Intel has participated in the establishment of the UCIe standard, with a view to building an ecosystem around Chiplet technology, which is crucial to its IDM2.0 strategic upgrade.
From a cost advantage point of view, although AMD and Intel have proven that multi-chip architectures have certain economics, in fact, compared to miniaturized transistors, chip glue does not always bring the greatest cost advantage .
Feng Yinxiao, a doctoral student at the Interdisciplinary College of Tsinghua University, and Ma Kaisheng, an assistant professor at the Interdisciplinary College of Tsinghua University
It was found that the current chiplets solution is only profitable on a large chip of 800 square millimeters, and the more advanced the process, the more obvious the benefit effect. For 5nm system-on-a-chip, multi-chip architectures only start to pay off when production reaches 20 million.
Not all chips are suitable for the chiplet method. Do not split for the sake of splitting. In many cases, a single integrated system-on-chip (SoC), such as an IoT SoC based on the FD-SOI process integrating radio frequency wireless connectivity, is more valuable.
Tablet PC application processing, autonomous driving domain processor, and data center application processor will be the three areas where Chiplet will take the lead. It is also the driving force for solving the problem of chiplet ‘chicken’ and ‘egg’.
That is to say, although Chiplet has the ability to continue Moore’s Law, for the vast majority of less advanced chip companies, there is no need to pay for the chip glue early on. Therefore, it is understandable why the UCIe Industry Alliance was jointly built by several chip giants.
However, it is undeniable that the upgrade of performance, power consumption and area is still the goal of the chip industry. will not be far away.
There will be a day, but when the reuse ability of chip universal glue reaches a certain level, it will be able to completely defeat transistor integration.
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