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ASML CTO believes that the current lithography technology may come to an end


ASML CTO believes that the current lithography technology may come to an end: 
High-NA EUV could be the end point.

In recent years, ASML has stood at the center of the world’s semiconductor technology.

ASML raised its production target twice last year, hoping that by 2025, its annual shipments will reach about 600 DUV (deep ultraviolet) lithography machines and 90 EUV (extreme ultraviolet) lithography machines.

Delivery problems occur every day due to the ongoing chip shortage, and ASML has encountered surprises like the fire at its Berlin factory.

A few days ago, ASML CTO Martin van den Brink accepted an interview with Bits & Chips .


ASML CTO believes that the current lithography technology may come to an end:  High-NA EUV could be the end point


According to Martin van den Brink, the biggest challenge in developing High-NA EUV technology was building a metrology tool for EUV optics, with mirrors twice the size of previous products, while keeping their flatness to within 20 picometers.

This need to be validated in a “half a company” vacuum vessel at Zeiss, a key optics partner for ASML’s advancement of High-NA EUV technology, which was added later.


At present, ASML is executing its roadmap in an orderly manner, and it is progressing smoothly.

After EUV is High-NA EUV technology.

ASML is preparing for the delivery of the first High-NA EUV lithography machine for customers, which will probably be completed at some point next year.

While supply chain issues could still disrupt ASML’s schedule, it shouldn’t be that big of a problem.

High-NA EUV lithography machines are more power-hungry than existing EUV lithography machines, increasing from 1.5 megawatts to 2 megawatts.

The main reason is because of the light source, High-NA uses the same light source that requires an additional 0.5 MW, and ASML also uses water-cooled copper wire to power it.


The outside world also wants to know the successor after High-NA EUV technology.

Jos Benschop, vice president of technology at ASML, revealed at last year’s SPIE advanced lithography conference a possible alternative, reducing the wavelength.

There are a few issues to solve with this solution, however, because the efficiency with which EUV mirrors reflect light is largely dependent on the angle of incidence, and a reduction in wavelength changes the angular range so that the lens must become too large to compensate, a phenomenon that also appears as the numerical aperture increases.


Martin van den Brink confirmed that ASML is working on this, but personally, we suspect that Hyper-NA will be the last NA, and it won’t necessarily make it into production, which means that after decades of lithography innovation, we may will come to the end of the current road of semiconductor lithography technology.

The main goal of ASML’s Hyper-NA research program is to come up with smart solutions that keep the technology manageable in terms of cost and manufacturability.


ASML CTO believes that the current lithography technology may come to an end:  High-NA EUV could be the end point



The High-NA EUV system will provide a 0.55 numerical aperture, with improved accuracy compared to previous EUV systems with 0.33 numerical aperture lenses, enabling higher resolution patterning for smaller transistor features.

In the hyper-NA system, it will be higher than 0.7, or even 0.75, which is theoretically possible.


Martin van den Brink does not want to create a larger “monster”. It is expected that hyper-NA may be the next problem in the development of semiconductor lithography technology, and its manufacturing and use costs will be staggeringly high.

If the manufacturing cost of Hyper-NA technology is increasing at the same rate as the current High-NA EUV technology, then it is almost infeasible economically. For now, what Martin van den Brink hopes to overcome is cost.


Transistor shrinkage is slowing due to potentially insurmountable cost constraints.

Thanks to advances in system integration, it’s still worthwhile to continue developing new generations of chips, which is good news.

At this point, the question becomes very real: Which chip structures are too small to be manufactured economically?