December 3, 2021

COSFONE SYSTEM

Networking Equipment, Telecom Equipment, Ethernet Cables, Connectors, Tools

AMD Zen 4 architecture details exposed: Secondary cache doubled

AMD Zen 4 architecture details exposed: Secondary cache doubled

AMD Zen 4 architecture details exposed: Secondary cache doubled. 

 

In the face of Intel’s just-released Alder Lake 12th-generation Core processor, the Ryzen 5000 based on the Zen3 architecture still has the power to fight in some scenarios, but for consumers, it is obviously Zen4 that is more expected.

According to the current rhythm, Zen4 should debut in the second half of next year, during which AMD may update the 6nm Zen3+ APU and part of the Ryzen 5000 CPU based on Zen3 3D cache technology.

AMD Zen 4 architecture details exposed: Secondary cache doubled

A few days ago, industry insider Hans de Vries exposed some of the details of the CPU design architecture of Zen 4, which is said to come from a confidential document leaked to the black market after a ransomware attack by a major hardware manufacturer not long ago.

 

The icon outlines the cache part of Zen 4. Compared with Zen3, the size of the first-level instruction/data cache has not changed, it is still 32KB, and the associated 8-way, but the second-level cache (instruction + data) is doubled from 512KB to 1MB, which is still associated with 8. road.

 

Unfortunately, the capacity of the three-level cache has not been announced. It seems to be a surprise. The previous generation of Zen3 shared 32MB for each CCD (8-core Die).

 

However, you can compare the 12th-generation Core Alder Lake system. Golden Cove (P core, performance core) has 1.25MB L2 cache per core, and Gracemont (energy efficiency core, E core) has 2MB per four cores, which is the second level cache. Up to 14MB, which means that the physical 16 cores (16MB L2) of Zen4 will surpass again.

 

AMD Zen 4 architecture details exposed: Secondary cache doubled

 

As for the 11th generation Core, there are no heterogeneous cores, and the secondary cache of each core is 0.5MB.

 

Generally speaking, level one and level two cache play an extremely important role in branch prediction, and it is also an important support for the increase in IPC indicators.

According to AMD’s previous statement, Zen4’s change to Zen3 will not be less than Zen3’s to Zen2. The IPC of the latter increased by 19% at that time. The 5nm Zen4 is very promising, and there is a late-comer advantage.

 

 

 

 

 


Leave a Reply