5.7GHz 128-core processor turned out: Power consumption approaching 1000W
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5.7GHz 128-core processor turned out: Power consumption approaching 1000W.
A few days ago, Silicon Valley start-up chip company Tachyum announced a magical processor “Prodigy”, known as the world’s first “universal processor” , with up to 128 cores and a frequency of up to 5.7GHz , which is really incredible.
Now, more details come.
The Tachyum Prodigy processor adopts a self-developed architecture, a 64-bit VLIW architecture core, and executes sequentially, but it can also perform 4-way out-of-order execution after compiler optimization.
Each core has another two 1024-bit vector units, a 4096-bit matrix unit, 64KB L1 instruction cache, 64KB L1 data cache, 1MB L2 cache, and the idle L2 cache can also be used by other cores as L3 cache.
The top model “Prodigy T16128-AIX”, with a frequency of up to 5.7GHz, supports 16-channel DDR5-7200 memory, with a maximum capacity of 8TB, also supports 64 PCIe 5.0, and consumes up to 950W.
It must be liquid-cooled for heat dissipation.
It is mainly aimed at high-end AI and HPC fields, with AI inference training performance of 12PFlops (120 billion calculations per second), FP64 HPC computing performance of 90TFlops (90 trillion calculations per second) – AMD RISC-V MI250X computing card can run up to 96TFlops, and only 560W.
It supports two- way and four-way parallelism , that is, a single system can achieve up to 512 cores and 32TB of memory.
The other three 128 cores are called T16128-AIM, T16128-AIE, and T16128 -HT.
The frequencies are 4.5GHz, 4.0GHz, and 4.5GHz , respectively . -6400.
There are two types of 64 cores , T864-HS and T864-HT, with frequencies of 5.7GHz and 4.5GHz respectively , supporting eight-channel DDR5-6400, 32 PCIe 5.0, and power consumption of 300W .
There are also two types of 32 cores , T832-HS and T832-LP, with frequencies of 5.7GHz and 3.2GHz respectively .
The memory frequency of the latter is reduced to DDR5-4800, and the power consumption is 300W and 180W respectively .
However, Tachyum has not yet had a silicon wafer. If everything goes well, it is expected to complete the tape-out in mid-August.
Using the TSMC N5P 5nm enhanced version, the core area is estimated to be no more than 500 square millimeters. The first silicon wafer will be obtained in December.
This time the live show is still a platform simulated by FPGA, with four simulated eight cores.
Even if the first generation is still on PPT, Tachyum has begun to look forward to the next generation: TSMC N3 3nm, supports PCIe 6.0, and doubles the performance under the same power consumption!
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